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Powerful tool to automate creating VHDL testbenches. Supports complex patterns and repeats to describe tests. Modular. Flexible - any variable can be include not just signals. Plot preview. Simulator displays descriptions as tests run.
Updated
Jul 20, 2004 16:24:29
Rating
299 ( -28 -9.36% )
Size
216 kb
Licence
Commercial
Status
Minor Update
Languages
English
Tags
VHDL, digital, testbench
OS
Windows 95, Windows 98, Windows ME, Windows NT, Windows 2000, Mac OS
LanMsg 1.01 — This program works with LanDial to control dialing / Hanging up a DUN over a LAN. As LanDial is useful on its own this program is a separate zip.
LanDial 1.03 — This program can be set to call divert number before dialing DUN and call a cancel number after so it works in UK etc. Also allows control of DUN dial / hangup over LAN with companion program LanMsg.
Description: Full Circuit releases greatly enhanced 'TestBench Tool':
Easily create testbenches (VHDL) with this low cost but powerful tool.
AUTOMATIC
Extracts entity from VHDL source and creates testbench VHDL source. Fills in signal names on tool so that all the user has to do is construct the test patterns.
FAST
Testbench VHDL source is not changed each time a test is revised (Test patterns are saved to a test vector file) so VHDL is only compiled once.
POWERFUL
Supports complex formulae for describing signal relationships. Has repeat sub section and repeat section. Text entry and plot view. Description displays in simulator as each test is executed.
MODULAR
Tests can be constructed in sections and test vectors built from one or all sections.
FLEXIBLE
Testbench source is small and simple to allow easy user enhancement. User modifications are protected from change by tool. User can modify project testbench for local changes or template testbench for global changes (i.e. adding user functions).
Test vectors are not limited just to entity signals but can include variables and times. A typical use of this would be to pulse a clock line N times rather than have N vector file entries. Note that the clock line can still be a signal so the vectors can drive the clock directly at the change over for better control (i.e. use N-1 in variable). Another use could be to supply data where source is incomplete
LOW COST
80 GBP (+VAT if applicable). Demo and 30 day full functional trial version available.
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299 ( -28 -9.36% )
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